In general there are three different power rail options—a gate contact (CB) power rail, a metal layer (M1) power rail, or a source/drain contact (CA) power rail. The CB power rail as shown in FIG. 1 and the M1 power as shown in FIG. 2 are used extensively in 20 nanometer technology nodes. The CB power rail connects source and drain through CA to M1. Working up from the substrate (not shown for illustrative convenience) a CB power rail cell includes diffusion regions (RXs) 101 and 103, polysilicon gate electrodes (PCs) 105, gate cut regions (CTs) 107, CB power rails 109, 111, and 113, vertical CAs 115 and 117 connecting the CB power rails 109 and 111 with RXs 101 and 103, respectively; double patterned vias (R0s) 119, 121, and 123 connecting the CB power rails 109, 111, and 113 to M1, i.e. to the positive power rails (VDDs) 125 and 127 in M1 and to the negative power rail (VSS) 129, respectively. The principle advantage of the CB power rail is that the R0s 119 through 123 are connected throughout the CB power rails 109 through 113, and the resulting redundancy ensures connectivity. In addition, there are no lithography limitations since the CB power rails 109 through 113 are not connected to other CBs. However, the principle disadvantage of the CB power rail is that the width of the CTs 107 must be greater than the width of the CB power rails 109 through 113 to prevent CB from shorting to PC. For example, CTs 107 are 94 nm in width as depicted as opposed to a minimum width of 44 nm. A further disadvantage is that the CB power rail scheme reduces RX efficiency in the cell.
As shown in FIG. 2, the M1 power rail functions much like any CA-R0-M1 connection wherein the source and drain are connected to CA and then to M1 through R0. More specifically, the M1 power rail cell, working up from the substrate, includes RXs 201 and 203, PCs 205, CTs 207, vertical CAs 209 and 211 connecting the R0s 213 and 215 to the RXs 201 and 203, respectively, and VDDs 217 and 219 in M1 and VSS 221, also in M1. The principle advantages of the M1 power rail is that the width of CT can be minimized thereby increasing the RX efficiency of the cell. However, the principle disadvantages are that there is no R0 redundancy, and, therefore, if R0 fails, the whole node will be floating. Also, the R0 enclosure of CA, e.g., R0 213 and CA 209, pushes the tip of CA 209 past the center of the M1 power rail 217, for example, which creates CA same color (same mask) space violations and forces the CAs within the cells to be pushed towards the middle causing congestion.
A need therefore exists for methodology enabling fabrication with CA power rails, with R0 redundancy, and minimum CT width, and the resulting device.